ATmega16U4 datasheet(268/408 Pages) ATMEL

268 / 408 page

268

7766D–AVR–01/09

ATmega16U4/ATmega32U4

• the UEINTX, UESTA0X and UESTA1X are restored to their reset value.

The data toggle field remains unchanged.

The other registers remain unchanged.

The endpoint configuration remains active and the endpoint is still enabled.

The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as

an answer to the CLEAR_FEATURE USB command.

22.4

USB reset

When an USB reset is detected on the USB line (SE0 state with a minimum duration of 2.5µs),

the next operations are performed by the controller:

• all the endpoints are disabled

• the default control endpoint remains configured (see Section 22.3, page 267 for more

details).

If the CPU hardware reset function is activated (RSTCPU bit set in UDCON register), a reset is

generated to the CPU core without disabling the USB controller (that follows the same behavior

than after a standard USB End of Reset, and remains attached). That feature may be used to

enhance device reliability.

22.5

Endpoint selection

Prior to any operation performed by the CPU, the endpoint must first be selected. This is done

by setting the EPNUM2:0 bits (UENUM register) with the endpoint number which will be man-

aged by the CPU.

The CPU can then access to the various endpoint registers and data.

22.6

Endpoint activation

The endpoint is maintained under reset as long as the EPEN bit is not set.

The following flow must be respected in order to activate an endpoint:

ATmega16U4 Datasheet(PDF) 268 Page - ATMEL Corporation