ATmega16U4 datasheet(265/408 Pages) ATMEL

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265

7766D–AVR–01/09

ATmega16U4/ATmega32U4

• 5 – FRZCLK: Freeze USB Clock Bit

Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power

consumption. Clear to enable the clock inputs.

• 4 – OTGPADE: VBUS Pad Enable

Set to enable the VBUS pad. Clear to disable the VBUS pad.

Note that this bit can be set/cleared even if USBE=0. That allows the VBUS detection even if the

USB macro is disable.

• 3-1 – Reserved

The value read from these bits is always 0. Do not set these bits.

• 0 – VBUSTE: VBUS Transition Interrupt Enable Bit

Set this bit to enable the VBUS Transition interrupt generation.

Clear this bit to disable the VBUS Transition interrupt generation.

• 7-2 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 1 - ID: ID status

This bit is always read as “1”, it has been conserved for compatibility with AT90USB64/128 (in

which it indicates the value of the OTG ID pin).

• 0 – VBUS: VBus Flag

The value read from this bit indicates the state of the VBUS pin. This bit can be used in device

mode to monitor the USB bus connection state of the application. See Section 21.9, page 263

for more details.

7-1 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 0 – VBUSTI: IVBUS Transition Interrupt Flag

Set by hardware when a transition (high to low, low to high) has been detected on the VBUS

pad.

Shall be cleared by software.

Bit

7654

----

VBUS

USBSTA

Read/Write

RRRR

Initial Value

0000

Bit

76543210

-------

VBUSTI

USBINT

Read/Write

RRRRRR

R/W

Initial Value

00000000

ATmega16U4 Datasheet(PDF) 265 Page - ATMEL Corporation

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