ATmega16U4 datasheet(261/408 Pages) ATMEL

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261

7766D–AVR–01/09

ATmega16U4/ATmega32U4

21.5.3

Freeze clock

The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which

freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the fol-

lowing registers:

• USBCON, USBSTA, USBINT

• UDCON (detach, ...)

•UDINT

•UDIEN

Moreover, when FRZCLK is set, only the following interrupts may be triggered:

• WAKEUPI

•VBUSTI

21.6

Speed Control

The speed selection (Full Speed or Low Speed) depends on the D+/D- pull-up. The LSM bit in

UDCON register allows to select an internal pull up on D+ (Low Speed mode) or D- (Full Speed

mode) data lines.

Figure 21-11. Device mode Speed Selection

21.7

Memory management

The controller only supports the following memory allocation management.

The reservation of a Pipe or an Endpoint can only be made in the increasing order (Pipe/End-

point 0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order.

The reservation of a Pipe or an Endpoint “k

i” is done when its ALLOC bit is set. Then, the hard-

ware allocates the memory and inserts it between the Pipe/Endpoints “ki-1” and “ki+1”. The “ki+1”

Pipe/Endpoint memory “slides” up and its data is lost. Note that the “k

i+2” and upper Pipe/End-

point memory does not slide.

Clearing a Pipe enable (PEN) or an Endpoint enable (EPEN) does not clear either its ALLOC bit,

or its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear

ALLOC. Then, the “k

i+1” Pipe/Endpoint memory automatically “slides” down. Note that the “ki+2”

and upper Pipe/Endpoint memory does not slide.

DETACH

UDCON.0

D+

D-

LSM

UDCON.2

UCAP

USB

Regulator

ATmega16U4 Datasheet(PDF) 261 Page - ATMEL Corporation

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