ATmega16U4 datasheet(289/408 Pages) ATMEL

289 / 408 page

289

7766D–AVR–01/09

ATmega16U4/ATmega32U4

• 7-0 - DAT7:0 -Data Bits

Set by the software to read/write a byte from/to the endpoint FIFO selected by EPNUM.

• 7-3 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 2-0 - BYCT10:8 - Byte count (high) Bits

Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is

provided by the UEBCLX register.

• 7-0 - BYCT7:0 - Byte Count (low) Bits

Set by the hardware. BYCT10:0 is:

- (for IN endpoint) increased after each writing into the endpoint and decremented after each

byte sent,

- (for OUT endpoint) increased after each byte sent by the host, and decremented after each

byte read by the software.

• 7 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 6-0 - EPINT6:0 - Endpoint Interrupts Bits

Set by hardware when an interrupt is triggered by the UEINTX register and if the corresponding

endpoint interrupt enable bit is set.

Cleared by hardware when the interrupt source is served.

Bit

76543

BYCT D10 BYCT D9

BYCT D8

UEBCHX

Read/Write

RRRR

Initial Value

00000

Bit

765432

BYCT D7

BYCT D6

BYCT D5

BYCT D4

BYCT D3

BYCT D2

BYCT D1

BYCT D0

UEBCLX

Read/Write

RRRRRRRR

Initial Value

000000

Bit

654321

EPINT D6

EPINT D5

EPINT D4

EPINT D3

EPINT D2

EPINT D1

EPINT D0 UEINT

Read/Write

RRRRR

Initial Value

000000

ATmega16U4 Datasheet(PDF) 289 Page - ATMEL Corporation

ATmega16U4 Datasheet(HTML) 289 Page - ATMEL Corporation

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