ATmega3290P datasheet(145/385 Pages) ATMEL

145 / 385 page

145

8021E–AVR–07/09

ATmega329P/3290P

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 16-6. The TCNT2 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2A and TCNT2.

Figure 16-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.

Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM2A1:0 to three (See Table 16-4 on page 153). The actual

OC2A value will only be visible on the port pin if the data direction for the port pin is set as out-

put. The PWM waveform is generated by setting (or clearing) the OC2A Register at the compare

match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at the timer

clock cycle the counter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0

bits.)

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

fOCnxPWM

clk_I/O

N 256

⋅

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ATmega3290P Datasheet(PDF) 145 Page - ATMEL Corporation