ATmega3290P datasheet(149/385 Pages) ATMEL

149 / 385 page

149

8021E–AVR–07/09

ATmega329P/3290P

Figure 16-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f

clk_I/O/8)

16.9

Asynchronous Operation of Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A

safe procedure for switching clock source is:

Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2.

Select clock source by setting AS2 as appropriate.

Write new values to TCNT2, OCR2A, and TCCR2A.

To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.

Clear the Timer/Counter2 Interrupt Flags.

Enable interrupts, if needed.

• The CPU main clock frequency must be more than four times the Oscillator frequency.

• When writing to one of the registers TCNT2, OCR2A, or TCCR2A, the value is transferred to a

temporary register, and latched after two positive edges on TOSC1. The user should not write

a new value before the contents of the temporary register have been transferred to its

destination. Each of the three mentioned registers have their individual temporary register,

which means that e.g. writing to TCNT2 does not disturb an OCR2A write in progress. To

detect that a transfer to the destination register has taken place, the Asynchronous Status

• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,

OCR2A, or TCCR2A, the user must wait until the written register has been updated if

Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if the Output Compare2 interrupt

is used to wake up the device, since the Output Compare function is disabled during writing to

OCR2A or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the

OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the

MCU will not wake up.

• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction

mode, precautions must be taken if the user wants to re-enter one of these modes: The

interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and reentering

sleep mode is less than one TOSC1 cycle, correct interrupt handling is not guaranteed. If the

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

ATmega3290P Datasheet(PDF) 149 Page - ATMEL Corporation

ATmega3290P Datasheet(HTML) 149 Page - ATMEL Corporation

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