ATmega3290P datasheet(152/385 Pages) ATMEL

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152

8021E–AVR–07/09

ATmega329P/3290P

16.10 Register Description

16.10.1

TCCR2A – Timer/Counter Control Register A

• Bit 7 – FOC2A: Force Output Compare A

The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-

ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when

operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare

match is forced on the Waveform Generation unit. The OC2A output is changed according to its

COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the

value present in the COM2A1:0 bits that determines the effect of the forced compare.

A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR2A as TOP.

The FOC2A bit is always read as zero.

• Bit 6, 3 – WGM21:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP)

counter value, and what type of waveform generation to be used. Modes of operation supported

by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and

two types of Pulse Width Modulation (PWM) modes. See Table 16-2 and ”Modes of Operation”

on page 143.

Note:

1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.

However, the functionality and location of these bits are compatible with previous versions of

the timer.

• Bit 5:4 – COM2A1:0: Compare Match Output Mode A

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be

set in order to enable the output driver.

Bit

210

(0xB0)

FOC2A

WGM20

COM2A1

COM2A0

WGM21

CS22

CS21

CS20

TCCR2A

Read/Write

R/W

Initial Value

Table 16-2.

Waveform Generation Mode Bit Description

(1)

Mode

WGM21

(CTC2)

WGM20

(PWM2)

Timer/Counter Mode of

Operation

TOP

Update of

OCR2A at

TOV2 Flag

Set on

Normal

0xFF

Immediate

MAX

PWM, Phase Correct

0xFF

TOP

BOTTOM

CTC

OCR2A

Immediate

MAX

Fast PWM

0xFF

BOTTOM

MAX

ATmega3290P Datasheet(PDF) 152 Page - ATMEL Corporation

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