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ATmega3290P Datasheet(PDF) 228 Page - ATMEL Corporation

Part # ATmega3290P
Description  8-bit Microcontroller with 32K Bytes In-System Programmable Flash
PDF  385 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATmega3290P Datasheet(HTML) 228 Page - ATMEL Corporation

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228
8021E–AVR–07/09
ATmega329P/3290P
Figure 22-1. LCD Module Block Diagram
22.2.2
LCD Clock Sources
The LCD Controller can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
LCD is by default equal to the system clock, clkI/O. When the
LCDCS bit in the LCDCRB Register is written to logic one, the clock source is taken from the
TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC voltage
offset across LCD segments.
22.2.3
LCD Prescaler
The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The LCDPS2:0 bits
selects clk
LCD divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock further by
1 to 8.
Output from the clock divider clk
LCD_PS is used as clock source for the LCD timing.
22.2.4
LCD Memory
The display memory is available through I/O Registers grouped for each common terminal.
When a bit in the display memory is written to one, the corresponding segment is energized (on),
and non-energized when a bit in the display memory is written to zero.
Clock
Multiplexer
12-bit Prescaler
0
1
Divide by 1 to 8
LCD
Timing
LCDCRB
LCDFRR
clk
i/o
TOSC
LCDCRA
D
A
T
A
B
U
S
Analog
Switch
Array
lcdcs
lcdcd2:0
lcdps2:0
clk
LCD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG35
SEG36
SEG37
SEG38
SEG39
COM0
COM1
COM2
COM3
LCD Buffer/
Driver
V
LCD
LCDDR 19 -15
LCDDR 14 -10
LCDDR 9 - 5
LCDDR 4 - 0
LATCH
array
LCD Ouput
Decoder
LCDCCR
lcdcc3:0
Contrast Controller/
Power Supply
clk
LCD_PS
LCD
CAP
40 x
4:1
MUX
LCD_voltage_ok
1/3 V
LCD
1/2 V
LCD
2/3 V
LCD
LCD Display Configuration
lcddc2:0



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