ATmega3290P datasheet(229/385 Pages) ATMEL

229 / 385 page

229

8021E–AVR–07/09

ATmega329P/3290P

To energize a segment, an absolute voltage above a certain threshold must be applied. This is

done by letting the output voltage on corresponding COM pin and SEG pin have opposite phase.

For display with more than one common, one (1/2 bias) or two (1/3 bias) additional voltage lev-

els must be applied. Otherwise, non-energized segments on COM0 would be energized for all

non-selected common.

Addressing COM0 starts a frame by driving opposite phase with large amplitude out on COM0

compared to none addressed COM lines. Non-energized segments are in phase with the

addressed COM0, and energized segments have opposite phase and large amplitude. For

waveform figures refer to ”Mode of Operation” on page 230. Latched data from LCDDR4 -

LCDDR0 is multiplexed into the decoder. The decoder is controlled from the LCD timing and

sets up signals controlling the analog switches to produce an output waveform. Next, COM1 is

addressed, and latched data from LCDDR9 - LCDDR5 is input to decoder. Addressing continu-

ous until all COM lines are addressed according to number of common (duty). The display data

are latched before a new frame start.

22.2.5

LCD Contrast Controller/Power Supply

The peak value (V

LCD) on the output waveform determines the LCD Contrast. VLCD is controlled

by software from 2.6V to 3.35V independent of V

CC. An internal signal inhibits output to the LCD

until V

LCD has reached its target value.

22.2.6

LCDCAP

An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-

ure 22-2. This capacitor acts as a reservoir for LCD power (V

LCD). A large capacitance reduces

ripple on V

LCD but increases the time until VLCD reaches its target value.

Figure 22-2. LCDCAP Connection

22.2.7

LCD Buffer Driver

Intermediate voltage levels are generated from buffers/drivers. The buffers are active the

amount of time specified by LCDDC[2:0] in LCDCCR. Then LCD output pins are tri-stated and

buffers are switched off. Shortening the drive time will reduce power consumption, but displays

with high internal resistance or capacitance may need longer drive time to achieve sufficient

contrast.

22.2.8

Display requirements

When using more than one common pin, the maximum period the LCD drivers can be turned on

for each voltage transition on the LCD pins is 50% of the prescaled LCD clock period, clk

LCD_PS.

To avoid flickering, it is recommended to keep the framerate above 30Hz, thus giving a maxi-

mum drive time of approximately 2ms when using 1/2 or 1/4 duty, and approximately 2.7ms

ATmega3290P Datasheet(PDF) 229 Page - ATMEL Corporation

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