ATmega3290P datasheet(307/385 Pages) ATMEL

307 / 385 page

307

8021E–AVR–07/09

ATmega329P/3290P

Figure 26-8. Parallel Programming Timing, Loading Sequence with Timing Requirements

(1)

Note:

1. The timing requirements shown in Figure 26-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-

ing operation.

Figure 26-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with

Timing Requirements

(1)

Note:

1. The timing requirements shown in Figure 26-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-

ing operation.Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). After RESET is set low, the Programming Enable instruction needs to be executed first

before program/erase operations can be executed. NOTE, in Table 26-14 on page 308, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal

SPI interface.

XTAL1

PAGEL

PLXH

XLXH

XLPH

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

XTAL1

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

ATmega3290P Datasheet(PDF) 307 Page - ATMEL Corporation

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