ATmega644PA datasheet(242/468 Pages) ATMEL

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242

8152G–AVR–11/09

ATmega164PA/324PA/644PA/1284P

22. ADC - Analog-to-digital Converter

22.1

Features

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

• ±2 LSB Absolute Accuracy

• 13 - 260 µs Conversion Time

• Up to 15 kSPS at Maximum Resolution

• 8 Multiplexed Single Ended Input Channels

• Differential mode with selectable gain at 1x, 10x or 200x

• Optional Left adjustment for ADC Result Readout

• 0 - V

CC ADC Input Voltage Range

• 2.7 - V

CC Differential ADC Voltage Range

• Selectable 2.56V or 1.1V ADC Reference Voltage

• Free Running or Single Conversion Mode

• ADC Start Conversion by Auto Triggering on Interrupt Sources

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

Note:

1. The differential input channels are not tested for devices in PDIP Package. This feature is only

guaranteed to work for devices in TQFP, VQFN/QFN/MLF, VFBGA and DRQFN Packages.

22.2

Overview

The ATmega164PA/324PA/644PA/1284P features a 10-bit successive approximation ADC. The

ADC is connected to an 8-channel Analog Multiplexer which allows 8 single-ended voltage

inputs constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND).

The device also supports 16 differential voltage input combinations. Two of the differential inputs

(ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage. This provides

amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage

before the A/D conversion. Seven differential analog input channels share a common negative

terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x

or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 6-bit resolution can be

expected. Note that internal references of 1.1V should not be used on 10x and 200x gain.

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 22-1

on page 243.

The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than

±0.3 V from V

CC. See the paragraph ”ADC Noise Canceler” on page 250 on how to connect this

pin.

Internal reference voltages of nominally 1.1V, 2.56V or AVCC are provided On-chip. The voltage

reference may be externally decoupled at the AREF pin by a capacitor for better noise perfor-

mance. If V

CC is below 2.1V, internal voltage reference of 1.1V should not be used on single

ended channels.

ATmega644PA Datasheet(PDF) 242 Page - ATMEL Corporation

ATmega644PA Datasheet(HTML) 242 Page - ATMEL Corporation

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