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ATmega644PA Datasheet(PDF) 240 Page - ATMEL Corporation |
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ATmega644PA Datasheet(HTML) 240 Page - ATMEL Corporation |
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240 / 468 page  240 8152G–AVR–11/09 ATmega164PA/324PA/644PA/1284P 21.3 Register Description 21.3.1 ADCSRB – ADC Control and Status Register B • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ”Analog Comparator Multiplexed Input” on page 239. 21.3.2 ACSR – Analog Comparator Control and Status Register • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar- ator. When bandgap reference is used as input to the Analog Comparator, it will take a certain time for the voltage to stabilize. If not stabilized, the first conversion may give wrong value. See ”Internal Voltage Reference” on page 55. • Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. 10 001 ADC1 10 010 ADC2 10 011 ADC3 10 100 ADC4 10 101 ADC5 10 110 ADC6 10 111 ADC7 Table 21-1. Analog Comparator Mulitiplexed Input ACME ADEN MUX2..0 Analog Comparator Negative Input Bit 7 65 432 10 (0x7B) – ACME – – - ADTS2 ADTS1 ADTS0 ADCSRB Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 76543210 0x30 (0x50) ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 00000 |
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