ATA6833 datasheet(13/27 Pages) ATMEL

13 / 27 page

9122D–AUTO–09/09

ATA6833/ATA6834 [Preliminary]

Figure 3-7.

Definition of Bus Timing Parameters

The recessive BUS level is generated from the integrated 30 k

Ω pull-up resistor in series with an

active diode. This diode protects against reverse currents on the bus line in case of a voltage dif-

ference between the bus line and VSUP (V

BUS > VSUP). No additional termination resistor is

necessary to use the IC as a LIN slave. If this IC is used as a LIN master, the LIN pin is termi-

nated by an external 1 k

Ω resistor in series with a diode to VBAT.

As PWM communication directly over the LIN transceiver in both directions is possible, there is

no TXD timeout feature implemented in the LIN transceiver.

TXD

(Input to transmitting node)

(Transceiver supply

of transmitting node)

RXD

(Output of receiving node1)

RXD

(Output of receiving node2)

LIN Bus Signal

Thresholds of

receiving node1

Thresholds of

receiving node2

tBus_rec(max)

trx_pdr(1)

trx_pdf(2)

trx_pdr(2)

trx_pdf(1)

tBus_dom(min)

tBus_dom(max)

THRec(max)

THDom(max)

THRec(min)

THDom(min)

tBus_rec(min)

tBit

ATA6833 Datasheet(PDF) 13 Page - ATMEL Corporation