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LTC3823IGN Datasheet(PDF) 15 Page - Linear Technology

Part # LTC3823IGN
Description  Fast No RSENSE Step-Down Synchronous DC/DC Controller with Differential Output Sensing, Tracking and PLL
PDF  26 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC3823IGN Datasheet(HTML) 15 Page - Linear Technology

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LTC3823
15
3823fd
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications 0.1μF to 0.47μF, X5R
or X7R dielectric capacitor is adequate.
Discontinuous Mode Operation and FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when in-
ductor current reverses. The load current at which current
reverses and discontinuous operation begins depends on
the amplitude of the inductor ripple current and will vary
with changes in VIN. Tying the FCB pin below the 0.6V
threshold forces continuous synchronous operation, al-
lowing current to reverse at light loads and maintaining
high frequency operation. To prevent forcing current back
into the main power supply, potentially boosting the input
supply to a dangerous voltage level, forced continuous
mode of operation is disabled when the TRACK/SS volt-
age is 20% below the reference voltage during soft-start
or tracking up. Forced continuous mode of operation is
also disabled when the TRACK/SS voltage is below 0.1V
during tracking down operation. During these two periods,
the PGOOD signal is forced low.
In addition to providing a logic input to forced continu-
ous operation, the FCB pin provides a mean to maintain
a flyback winding output when the primary is operating
in discontinuous mode. The secondary output VOUT2 is
normally set as shown in Figure 5 by the turns ratio N
of the transformer. However, if the controller goes into
discontinuous mode and halts switching due to a light
primary load current, then VOUT2 will droop. An external
resistor divider from VOUT2 to the FCB pin sets a minimum
voltage VOUT2(MIN) below which continuous operation is
forced until VOUT2 has risen above its minimum.
VV
R
R
OUT MIN
2
06
1
4
3
()
.
=+
⎛
⎝⎜
⎞
⎠⎟
Fault Conditions: Current Limit and Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3823, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
I
V
R
I
LIMIT
SNS MAX
DS ON
T
L
=+
()
() ρ
1
2
Δ
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET
on-resistance. Data sheets typically specify nominal
and maximum values for RDS(ON), but not a minimum.
A reasonable assumption is that the minimum RDS(ON)
lies the same percentage below the typical value as the
maximum lies above it. Consult the MOSFET manufacturer
for further guidelines.
To further limit current in the event of a short circuit to
ground, the LTC3823 includes foldback current limiting.
If the output falls by more than 60%, then the maximum
sense voltage is progressively lowered to about one tenth
of its full value.
APPLICATIONS INFORMATION
VIN
LTC3823
SGND
FCB
TG
SW
R3
R4
3823 F05
T1
1:N
BG
PGND
+
COUT2
1μF
VOUT1
VOUT2
VIN
+
CIN
1N4148
•
+
COUT
Figure 5. Secondary Output Loop



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