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LTC3823

3823fd

APPLICATIONS INFORMATION

Design Example

As a design example, take a supply with the following

speciﬁcations: VIN = 5V to 28V (15V nominal), VOUT =

2.5V ±5%, IOUT(MAX) = 10A, f = 320kHz. First, calculate

the timing resistor with VON = VOUT:

VkHz

ON =

()(

)( )

3 2 5

320

104

and choose the inductor for about 40% ripple current at

the maximum VIN:

kHz

= ()( )( ) −

⎛

⎝

⎜

⎞

⎠

⎟ =

320

0 4 10

7µH

Selecting a standard value of 1.2μH results in a maximum

ripple current of:

kHz

L =

()(

)

⎛

⎝

⎜

⎞

⎠

⎟ =

320

1 2

–

Next, choose the synchronous MOSFET switch. Choosing

a Si7892ADP (RDS(ON) = 0.005Ω (NOM) 0.006Ω (MAX),

θJA = 50°C/W) yields a nominal sense voltage of:

VSNS(NOM) = (7A)(1.3)(0.005Ω) = 45mV

Tying VRNG to0.75Vwillsetthecurrentsensevoltagerange

for a nominal value of 75mV with current limit occurring

at 100mV. To check if the current limit is acceptable, as-

sume a junction temperature of about 80°C above a 70°C

ambient with

ρ150°C = 1.5:

LIMIT ≥

()(

)

() =

100

15 0006

and double check the assumed TJ in the MOSFET:

BOT =

() ( )(

) =

15 0 006

–.

TJ = 70°C + (1.6W)(50°C/W) = 150°C

Because the top MOSFET is on for such a short time,

an Si7342DP RDS(ON)(MAX) = 0.010Ω, CRSS = 120pF,

θJA=53°C/Wwillbesufﬁcient.Checkingitspowerdissipa-

tion at current limit with

ρ100°C=1.4:

TOP =

() ( )

()+

()( )

1 4 0 010

17 28

120

320

025

0 72

097

ApF

kHz

()(

)(

)

=+=

TJ = 70°C + (0.97W)(53°C/W) = 121°C

The junction temperature will be signiﬁcantly less at

nominal current, but this analysis shows that careful at-

tention to heat sinking on the board will be necessary in

this circuit.

CIN is chosen for an RMS current rating of about 3A at

85°C. The output capacitors are chosen for a low ESR

of 0.013Ω to minimize output voltage changes due to

inductor ripple current and load steps. The ripple voltage

will be only:

ΔVOUT(RIPPLE) = ΔIL(MAX) (ESR)

= (5.9A) (0.013Ω) = 77mV

However, a 0A to 10A load step will cause an output

change of up to:

ΔVOUT(STEP) = ΔILOAD (ESR) = (10A) (0.013Ω) = 130mV

An optional 22μF ceramic output capacitor is included

to minimize the effect of ESL in the output ripple. The

complete circuit is shown in Figure 12.

PC Board Layout Checklist

When laying out a PC board follow one of two suggested

approaches. The simple PC board layout requires a ded-

icated ground plane layer. Also, for higher currents, it is

recommended to use a multilayer board to help with heat

sinking power components.

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power

MOSFETs.

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