LTC3823IGN datasheet(18/26 Pages) LINER

18 / 26 page

LTC3823

3823fd

Differential Ampliﬁer

This ampliﬁer provides true differential output voltage

sensing. Sensing both the positive and negative terminals

of the output voltage beneﬁts regulation in high current

applications and/or applications having electrical intercon-

nection losses. Precision feedback resistors are integrated

in the IC with the ampliﬁer already conﬁgured as a unity-gain

differential ampliﬁer. It has a GBW product of 3.5MHz and

an open-loop gain of >120dB. The ampliﬁer can source

>2mA of current, and can be used in applications with

up to 3.3V output voltage. The ampliﬁer is not capable of

sinking signiﬁcant current, and must be resistively loaded.

A load of 20kΩ or less is recommended for stability. The

ampliﬁer is not designed to drive capacitive loads.

Phase-Locked Loop and Frequency Synchronization

The LTC3823 has a phase-locked loop comprised of an

internal voltage controlled oscillator and phase detector.

This allows the top MOSFET turn-on to be locked to the

rising edge of an external source. The frequency range

of the voltage controlled oscillator is ±30% around the

center frequency, fO. The center frequency is the operat-

ing frequency discussed in the previous section. The

LTC3823 incorporates a pulse detection circuit that will

detect a clock on the PLLIN pin. In turn, it will turn on the

phase-locked loop function. The pulse width of the clock

has to be greater than 400ns and the amplitude of the

clock should be greater than 2V.

During the start-up phase, phase-locked loop function is

disabled. When LTC3823 is not in synchronization mode,

PLLFLTR pin voltage is set to around 1.18V. Frequency

synchronization is accomplished by changing the internal

on-time current according to the voltage on the PLLFLTR

pin.

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the ex-

ternal and internal pulses. This type of phase detector will

not lock up on input frequencies close to the harmonics

of the VCO center frequency. The PLL hold-in range, ΔfH,

is equal to the capture range, ΔfC:

ΔfH = ΔfC = ±0.3 fO

The output of the phase detector is a complementary pair of

current sources charging or discharging the external ﬁlter

network on the PLLFLTR pin. A simpliﬁed block diagram

is shown in Figure 10.

If the external frequency (fPLLIN) is greater than the oscil-

lator frequency fO, current is sourced continuously, pull-

ing up the PLLFLTR pin. When the external frequency is

less than fO, current is sunk continuously, pulling down

the PLLFLTR pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. Thus the voltage on the PLLFLTR

pin is adjusted until the phase and frequency of the external

and internal oscillators are identical. At this stable operating

point the phase comparator output is open and the ﬁlter

capacitor CLP holds the voltage. The LTC3823 PLLIN pin

must be driven from a low impedance source such as a

logic gate located close to the pin.

The loop ﬁlter components (CLP, RLP) smooth out the cur-

rent pulses from the phase detector and provide a stable

input to the voltage controlled oscillator. The ﬁlter compo-

nents CLP and RLP determine how fast the loop acquires

lock. Typically RLP =10k and CLP is 0.01μF to 0.1μF.

Dead Time Control

To further optimize the efﬁciency, the LTC3823 gives us-

ers some control over the dead time of the Top gate low

and Bottom gate high transition. By applying a DC voltage

on the Z0 pin, the TG low BG high dead time can be pro-

grammed. Because the dead time is a strong function of

APPLICATIONS INFORMATION

DIGITAL

PHASE/

FREQUENCY

DETECTOR

PLLIN

PLLFLTR

2.4V

CLP

3823 F10

RLP

VCO

Figure 10. Phase-Locked Loop Block Diagram

LTC3823IGN Datasheet(PDF) 18 Page - Linear Technology

LTC3823IGN Datasheet(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL