78Q2133SLASHF datasheet(13/42 Pages) TERIDIAN

13 / 42 page

78Q2123/78Q2133 MicroPHY™

10/100BASE-TX Transceiver

Page: 13 of 42

Rev 1.5

MR1: Status Register

Bits 1.15 through 1.11 reflect the ability of the 78Q2123/78Q2133. They do not reflect any ability changes made

via the MII Management interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and 0.8 (DUPLEX) in the Control

BIT

SYMBOL

TYPE DEFAULT DESCRIPTION

1.15

100T4

100BASE-T4 Ability: Reads ‘0’ to indicate the 78Q2123/78Q2133 do

not support 100Base-T4 mode.

1.14

100X_F

100BASE-TX Full Duplex Ability:

0 : Not able

1 : Able

1.13

100X_H

100BASE-TX Half Duplex Ability:

0 : Not able

1 : Able

1.12

10T_F

10BASE-T Full Duplex Ability:

0 : Not able

1 : Able

1.11

10T_H

10BASE-T Half Duplex Ability:

0 : Not able

1 : Able

1.10

100T2_F

100BASE-T2 Full Duplex Ability:

Reads ‘0’ to indicate the

78Q2123/78Q2133 do not support 100Base-T2 full duplex mode.

1.9

100T2_H

100BASE-T2 Half Duplex Ability:

Reads ‘0’ to indicate the

78Q2123/78Q2133 do not support 100Base-T2 full duplex mode.

1.8

EXTS

Extended Status Information Availability: Reads ‘0’ to indicate the

78Q2123/78Q2133 do not support Extended Status information on

MR15.

1.7

RSVD

Reserved

1.6

MFPS

Management Frame Preamble Suppression Support: A “0” indicates

that the 78Q2123/78Q2133 can read management frames with a

preamble.

1.5

ANEGC

Auto-Negotiation Complete:

A logic one indicates that the Auto-

Negotiation process has been completed, and that the contents of

registers MR4,5,6 are valid.

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