78Q2133SLASHF datasheet(2/42 Pages) TERIDIAN

2 / 42 page

78Q2123/78Q2133 MicroPHY™

10/100BASE-TX Transceiver

Page: 2 of 42

Rev 1.5

FUNCTIONAL DESCRIPTION

GENERAL

Power Management

The 78Q2123 and 78Q2133 have three power

saving modes:

•

Chip Power-Down

•

Receive Power Management

•

Transmit High Impedance Mode

Chip power-down is activated by setting the PWRDN

bit in MII register MR0.11.

When the chip is in

power-down mode, all on-chip circuitry is shut off,

and the device consumes minimum power. While in

the power-down state, the 78Q2123/78Q2133 still

respond to management transactions.

Receive power management (RXCC mode) is

activated by setting the RXCC bit in MII register

MR16.0. In this mode of operation, the adaptive

equalizer, the clock recovery phase lock loop (PLL),

and all other receive circuitry will be powered down

when no valid MLT-3 signal is present at the UTP

receive line interface. As soon as a valid signal is

detected, all circuits will automatically be powered

up to resume normal operation. During this mode of

operation, RX_CLK will be inactive when there is no

data being received. Note that the RXCC mode is

not supported during 10BASE-T operation.

Transmit high impedance mode is activated by

setting the TXHIM bit in MII register MR16.12. In this

mode of operation, the transmit UTP drivers are in a

high impedance state and TX_CLK is tri-stated. A

weak internal pull-up is enabled on TX_CLK. The

receive circuitry remains fully operational. The

default state of MR16.12 is a logic low for disabling

the transmit high impedance mode. Only a reset

condition will automatically clear MR16.12. The

transmitter is fully functional when MR16.12 is

cleared. This feature is useful when configuring a

system

for

Wake-On

LAN

(when

the

78Q2123/78Q2133 are coupled with a Wake-On

LAN capable MAC).

Analog Biasing and Supply Regulation

The

78Q2123/78Q2133

require

external

component to generate on-chip bias voltages and

currents. High accuracy is maintained through a

closed-loop trimmed biasing network.

On-chip digital logic runs off an internal voltage

regulator. Hence only a single 3.3V (

± 0.3V) supply

is required to power-up the device. The on-chip

regulator is not affected by the power-down mode.

Clock Selection

The 78Q2123/78Q2133 have an on-chip crystal

oscillator which can also be driven by an external

oscillator. In this mode of operation, a 25MHz crystal

should be connected between the XTLP and XTLN

pins.

Alternatively, an external 25MHz clock input

can be connected to the XTLP pin. In this mode of

operation, a crystal is not required and the XTLN pin

must be tied to ground.

Transmit Clock Generation

The

transmitter

uses

on-chip

frequency

synthesizer to generate the transmit clock. In

100BASE-TX operation, the synthesizer multiplies the

reference clock by 5 to obtain the internal 125MHz

serial transmit clock.

In 10BASE-T mode, it

generates an internal 20MHz transmit clock by

multiplying the reference 25MHz clock by 4/5. The

synthesizer references either the local 25 MHz crystal

oscillator, or the externally applied clock, depending

on the selected mode of operation.

Receive Signal Qualification

The integrated signal qualifier has separate squelch

and unsquelch thresholds. It also includes a built-in

timer to ensure fast and accurate signal detection and

line noise rejection. Upon detection of two or more

valid 10BASE-T or 100BASE-TX pulses on the line

receive port, signal detect is indicated. The signal

detect threshold is then lowered by about 40%. All

adaptive circuits are released from their initial states

and allowed to lock onto the incoming data.

100BASE-TX operation, signal detect is de-asserted

when no signal is presented for a period of about

1.2us. In 10BASE-T operation, signal detect is de-

asserted whenever no Manchester data is received. In

either case, the signal detect threshold will return to the

squelched level whenever the signal detect indication

is de-asserted. Signal detect is also used to control the

operation of the clock/data recovery circuit to assure

fast acquisition.

Receive Clock Recovery

In 100BASE-TX mode, the 125MHz receive clock is

extracted using a digital DLL-based loop. When no

receive signal is present, the CDR is directed to lock

onto the 125MHz transmit serial clock. When signal

detect is asserted, the CDR will use the received MLT-

3 signal as the clock reference. The recovered clock is

used to re-time the data signal and for conversion of

the data to NRZ format.

78Q2133/F Datasheet(PDF) 2 Page - Teridian Semiconductor Corporation

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