33926 datasheet(7/25 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33926

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 5.0 V

≤ VPWR ≤ 28 V, -40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUTS (VPWR)

Operating Voltage Range (10)

Steady-state

Transient (t < 500 ms) (11)

VPWR(SS)

VPWR(t)

5.0

–

Sleep State Supply Current (12)

EN, D2, INV, SLEW = Logic [0], IN1, IN2, D1 = Logic [1], and

IOUT = 0 A

IPWR(SLEEP)

–

μA

Standby Supply Current (Part Enabled)

IOUT = 0 A, VEN = 5.0 V

IPWR(STANDBY)

–

Under-voltage Lockout Thresholds

VPWR(FALLING)

VPWR(RISING)

Hysteresis

VUVLO(ACTIVE)

VUVLO(INACTIVE)

VUVLO(HYS)

4.15

–

150

–

200

–

5.0

350

CHARGE PUMP

Charge Pump Voltage (CP Capacitor = 33 nF)

VPWR = 5.0 V

VPWR = 28 V

VCP - VPWR

3.5

–

CONTROL INPUTS

Operating Input Voltage (EN, IN1, IN2, D1, D2, INV, SLEW)

–

5.5

Input Voltage (IN1, IN2, D1, D2, INV, SLEW) (13)

Logic Threshold HIGH

Logic Threshold LOW

Hysteresis

VIH

VIL

VHYS

2.0

–

250

–

400

–

1.0

–

Input Voltage (EN) Threshold

VTH

1.0

–

2.0

Logic Input Currents, VPWR = 5.0 V

Inputs EN, D2, INV, SLEW (internal pull-downs), VIH = 5.0 V

Inputs IN1, IN2, D1 (internal pull-ups), VIL = 0V

IIN

-200

-80

200

-20

μA

Notes

10.

Device specifications are characterized over the range of 8.0 V

≤ VPWR ≤ 28 V. Continuous operation above 28 V may degrade device

reliability. Device is operational down to 5.0 V, but below 8.0 V the output resistance may increase by 50 percent.

11.

Device will survive the transient overvoltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once

every 10 seconds.

12.

IPWR(SLEEP) is with Sleep mode activated and EN, D2, INV, SLEW = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.

13.

SLEW input voltage hysteresis is guaranteed by design.

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