33988 datasheet(24/34 Pages) FREESCALE

24 / 34 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33988

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

DEVICE REGISTER ADDRESSING

The following section describes the possible register

addresses and their impact on device operation.

Address x000—Status Register (STATR)

The STATR register is used to read the device status and

the various configuration register contents without disrupting

the device operation or the register contents. The register bits

D2:D0, determine the content of the first eight bits of SO data.

When register content is specific to one of the two outputs, bit

D7 is used to select the desired output (SOA3). In addition to

the device status, this feature provides the ability to read the

content of the OCR, SOCHLR, CDTOLR, DICR, OSDR,

WDR, NAR, and UOVR registers. (Refer to the section

entitled Serial Output Communication (Device Status Return

Data).)

Address x001—Output Control Register (OCR)

The OCR register allows the MCU to control the outputs

through the SPI. Incoming message bit D0 reflects the

desired states of the high side output HS0 (IN0_SPI): a

Logic [1] enables the output switch and a Logic [0] turns it

OFF. A Logic [1] on message bit D1 enables the Current

Sense (CSNS) pin. Similarly, incoming message bit D2

reflects the desired states of the high side output HS1

(IN1_SPI): Logic [1] enables the output switch and a Logic [0]

turns it OFF. A Logic [1] on message bit D3 enables the

CSNS pin. In the event that the current sense is enabled for

both outputs, the current will be summed. Bit D7 is used to

feed the watchdog if enabled.

Address x010— Select Over-current High and Low

The SOCHLR register allows the MCU to configure the

output over-current low and high detection levels,

respectively. Each output is independently selected for

configuration based on the state of the D7 bit; a write to this

detection levels for the HS0. Similarly, if D7 is Logic [1] when

this register is written, HS1 is configured. Each output can be

configured to different levels. In addition to protecting the

device, this slow blow fuse emulation feature can be used to

optimize the load requirements matching system

characteristics. Bits D2:D0 set the over-current low detection

level to one of eight possible levels, as shown in Table 10.

Bit D3 sets the over-current high detection level to one of two

levels, which is described inTable 11.

Address x011—Current Detection Time and Open Load

The CDTOLR register is used by the MCU to determine

the amount of time the device will allow an over-current low

condition before output latches OFF occurs. Each output is

independently selected for configuration based on the state

of the D7 bit. A write to this register when bit 7 is Logic [0] will

configure the timeout for the HS0. Similarly, if D7 is Logic [1]

when this register is written, then HS1 is configured. Bits

D1:D0 allow the MCU to select one of four fault blanking

times defined in Table 12. Note that these timeouts apply

only to the over-current low detection levels. If the selected

over-current high level is reached, the device will latch off

within 20μs.

A Logic [1] on bit D2 disables the over-current low

(CD_dis) detection timeout feature. A Logic [1] on bit D3

disables the open load (OL) detection feature.

Table 10. Over-current Low Detection Levels

SOCL2

(D2)

SOCL1

(D1)

SOCL0

(D0)

Over-current Low Detection

(Amperes)

12.5

11.25

10.0

8.75

7.5

6.25

5.0

3.75

Table 11. Over-current High Detection Levels

SOCH (D3)

Over-current High Detection

(Amperes)

37.5

Table 12. Over-current Low Detection Blanking Time

OCLT[1:0]

Timing

155ms

10ms

1.2ms

150

μs

33988 Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc

33988 Datasheet(HTML) 24 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL