33988 datasheet(25/34 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33988

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Address x100—Direct Input Control Register (DICR)

The DICR register is used by the MCU to enable, disable,

or configure the direct IN pin control of each output. Each

output is independently selected for configuration based on

the state of bit D7. A write to this register when bit D7 is

Logic [0] will configure the direct input control for the HS0.

Similarly, if D7 is Logic [1] when this register is written, then

HS1 is configured.

A Logic [0] on bit D1 will enable the output for direct control

by the IN pin. A Logic [1] on bit D1 will disable the output from

direct control. While addressing this register, if the input was

enabled for direct control, a Logic [1] for the D0 bit will result

in a Boolean AND of the IN pin with its corresponding D0

message bit when addressing the OCR register. Similarly, a

Logic [0] on the D0 pin results in a Boolean OR of the IN pin

with the corresponding message bits when addressing the

OCR register.

The DICR register is useful if there is a need to

independently turn on and off several loads that are PWM’d

at the same frequency and duty cycle with only one PWM

signal. This type of operation can be accomplished by

connecting the pertinent direct IN pins of several devices to a

PWM output port from the MCU and configuring each of the

outputs to be controlled via their respective direct IN pin. The

DICR is then used to Boolean AND the direct IN(s) of each of

the outputs with the dedicated SPI bit that also controls the

output. Each configured SPI bit can now be used to enable

and disable the common PWM signal from controlling its

assigned output.

A Logic [1] on bit D2 is used to select the high ratio (CSR1,

1/41000) on the CSNS pin for the selected output. The

default value [0] is used to select the low ratio (CSR0,

1/20500). A Logic [1] on bit D3 is used to select the high

speed slew rate for the selected output. The default value [0]

corresponds to the low speed slew rate.

Address 0101—Output Switching Delay Register (OSDR)

The OSDR register configures the device with a

programmable time delay that is active during Output ON

transitions initiated via SPI (not via direct input).

A write to this register configures both outputs for different

delay. Whenever the input is commanded to transition from

Logic [0] to Logic [1], both outputs will be held OFF for the

time delay configured in the OSDR. The programming of the

contents of this register have no effect on device Fail-safe

mode operation. The default value of the OSDR register is

000, equating to no delay. This feature allows the user a way

to minimize inrush currents, or surges, thereby allowing loads

to be switched ON with a single command. There are eight

selectable output switching delay times that range from 0ms

to 525ms. Refer to Table 13.

Address 1101—Watchdog Register (WDR)

The WDR register is used by the MCU to configure the

watchdog timeout. Watchdog timeout is configured using bits

D1:D0. When D1:D0 bits are programmed for the desired

watchdog timeout period, the WD bit (D7) should be toggled

as well, ensuring the new timeout period is programmed at

the beginning of a new count sequence. Refer to Table 14.

Address 0110—No Action Register (NAR)

The NAR register can be used to no-operation fill SPI data

packets in a daisy chain SPI configuration. This allows

devices to not be affected by commands being clocked over

a daisy-chained SPI configuration, and by toggling the WD bit

(D7), the watchdog circuitry will continue to be reset while no

programming or data readback functions are being requested

from the device.

Address 1110—Under-voltage/Over-voltage Register

(UOVR)

The UOVR register can be used to disable or enable over-

voltage and/or under-voltage protection. By default

(Logic [0]), both protections are active. When disabled, an

under-voltage or over-voltage condition fault will not be

reported in the output fault register.

Address x111—TEST

The TEST register is reserved for test and is not

accessible with the SPI during normal operation.

Table 13. Switching Delay

OSD[2:0] (D2:D0)

Turn ON Delay (ms)

HS0

Turn ON Delay (ms)

HS1

000

001

010

150

011

225

150

100

300

101

375

300

110

450

111

525

450

Table 14. Watchdog Timeout

WD[1:0] (D1:D0)

Timing (ms)

620

310

2500

1250

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