TLP512 datasheet(4/7 Pages) TOSHIBA

4 / 7 page

TLP512

2002-11-28

Switching Characteristics (Ta

= 25°C)

Characteristics

Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

Propagation delay time (H

® L)

tpHL

IF = 0 ® 16 mA, RL = 1.9 kW

0.8

Propagation delay time (L

® H)

tpLH

IF = 16 ® 0 mA, RL = 1.9 kW

0.8

Common mode transient immunity at

logic high output

(Note 8)

CMH

IF = 0 mA, VCM = 200 VP−P

RL = 1.9 kW

1500

Common mode transient immunity at

logic low output

(Note 8)

CML

IF = 16 mA, VCM = 200 VP−P

RL = 1.9 kW

-1500

Note 8: Common mode transient immunity in logic high level is the maximum tolerable (positive) dVCM/dt on the

leading edge of the common mode pulse, VCM, to assure that the output will remain in a logic high state

(VOUT > 2.0 V).

Common mode transient immunity in logic low level is the maximum tolerable (negative) dVCM/dt on the

trailing edge of the common mode pulse, VCM, to assure that the output will remain in a logic low state

(VOUT < 0.8 V).

Note 9: Electrostatic discharge immunity (pin to pin): 100 V (max)

£ 200 pF, R = 0)

Test Circuit 1: Switching Time Test Circuit

Test Circuit 2: Common Mode Noise Immunity Test Circuit

(

(V)

160

(

(V)

160

VCC = 5 V

Output monitor

VCM

Pulse generator

ZO = 50 W

VCM

200 V

(IF = 0 mA)

(IF = 16 mA)

0 V

5 V

2 V

0.8 V

VOL

10%

90%

tpHL

1.5 V

5 V

1.5 V

VOL

tpLH

VCC = 5 V

Output monitor

Pulse input

= 100 ms

Duty ratio

= 1/10

IF monitor

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