16950B datasheet(13/35 Pages) HP

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Agilent 16950B and 16951B Specifications and Characteristics

State (Synchronous) Analysis Mode

300 Mb/s State Mode

667 Mb/s State Mode

tWidth* [1, 2]

850 ps*, 550 ps typical

tSetup

0.5 tWidth

tHold

0.5 tWidth

tSample range [3]

–4 ns to +4 ns

tSample adjustment resolution

80 ps typical

tSample accuracy, manual adjustment

± 300 ps

± 300 ps [4]

Maximum state data rate

300 Mb/s (DDR)

667 Mb/s (DDR)

600 Mb/s (Dual sample)

1066 Mb/s (Dual sample)

Maximum channels on a single time base

340 – (number of clocks)

306 – (1 clock)

and trigger [5]

Memory depth – 16950B [5]

Option 001: 1 M samples

Option 004: 4 M samples

Option 016: 16 M samples

Option 032: 32 M samples

Option 064: 64 M samples

Memory depth – 16951B [5]

256 M samples

Number of independent analyzers [6]

Number of clocks [7]

Number of clock qualifiers [7]

N/A

Minimum time between active

3.33 ns

1.50 ns

clock edges* [8]

Minimum master to slave clock time

1 ns

N/A

Minimum slave to master clock time

1 ns

N/A

Minimum slave to slave clock time

3.33 ns

N/A

Items marked with an asterisk (*) are specifications. All others are characteristics.

[1] Minimum eye width in system under test.

[2] Your choice of probe can limit system bandwidth. Choose a probe rated at 1066 Mb/s or

greater to maintain system bandwidth.

[3] Sample positions are independently adjustable for each data channel input. A negative

sample position causes the input to be synchronously sampled by that amount before

each active clock edge. A positive sample position causes the input to be synchronously

sampled by that amount after each active clock edge. A sampling position of zero causes

the input to be synchronously sampled coincident with each clock edge.

[4] Use of eye finder is recommended in 667 Mb/s state mode.

[5] In 300 Mb/s state mode, with all pods assigned, memory depth is half the maximum

memory depth. With one pod pair (34 channels) unassigned, the memory depth is full. One

pod pair (34 channels) must remain unassigned for time tags in 667 Mb/s state mode.

[6] Independent analyzers may be either state or timing. When the 667 Mb/s state mode is

selected, only one analyzer may be used.

[7] In the 300 Mb/s state mode, the total number of clocks and qualifiers is 4. All clock and

qualifier inputs must be on the master modules.

[8] Tested with input signal Vh = +1.125 V, Vl = +0.875 V = 1 V/ns, threshold = +1.0 V,

tr/tf = 180 ps ± 30 ps (10%, 90%).

Clock Channel

Data Eye

vHeight

tWidth

vThreshold

tSetup tHold

tSample

Sampling Position

Individual

Data Channel

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