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16950B Datasheet(PDF) 21 Page - Agilent(Hewlett-Packard)

Part # 16950B
Description  Logic Analyzer
PDF  35 Pages
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Manufacturer  HP [Agilent(Hewlett-Packard)]
Direct Link  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

16950B Datasheet(HTML) 21 Page - Agilent(Hewlett-Packard)

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Agilent 16760A Specifications and Characteristics
Agilent Technologies 16760A Supplemental Specifications* and Characteristics (continued)
Synchronous State
Analysis [4] (continued) 1.5 Gb/s mode
1.25 Gb/s mode
800 Mb/s mode
400 Mb/s mode
200 Mb/s mode
Maximum trigger
22416
16
sequence levels
Maximum trigger
1.5 Gb/s
1.25 Gb/s
800 MHz
400 MHz
200 MHz
sequencer speed
Store qualification
Default
Default
Default
Default
Default and per
sequence level
Maximum
N/A
N/A
N/A
N/A
16,777,215
global counter
Maximum
N/A
N/A
N/A
N/A
16,777,215
occurrence counter
Maximum pattern/
32 bits [3]
32 bits [3]
32 bits [3]
32 bits [3]
32 bits [3]
range term width
Timer value range
N/A
N/A
N/A
N/A
100 ns to 4397 seconds
Timer resolution
N/A
N/A
N/A
N/A
4 ns
Timer accuracy
N/A
N/A
N/A
N/A
±(10 ns + 0.01% of
value)
Timer reset latency
N/A
N/A
N/A
N/A
65 ns
Data in to BNC port
150 ns
150 ns
150 ns
150 ns
150 ns
out latency
Flag set/reset to
N/A
N/A
N/A
N/A
110 ns
evaluation latency
[1] In 1.25 Gb/s and 1.5 Gb/s modes, only the even-numbered channels (0, 2, 4, etc.) are acquired.
[2] The resolution of the hardware used to assign time tags is 4 ns. Times of intermediate states are calculated.
[3] Maximum label width is 32 bits. Wider patterns can be created by “Anding” multiple labels together.
[4] The choice of probe can limit system performance. Select a probe rated at the speed of the selected mode (or greater) to maintain system bandwidth.
Asynchronous Timing Analysis
Conventional Timing Analysis
Transitional Timing Analysis
Maximum timing analysis sample rate
800 MHz
400 MHz
Number of channels
34 x (number of modules)
Sampling rates < 400 MHz: 34 x (number of modules)
Sampling rates = 400 MHz:
34 x (number of modules) – 17 [1]
Maximum channels on a
170 (5 modules)
170 (5 modules)
single time base and trigger
Sample period
1.25 ns
2.5 ns to 1 ms [1]
Memory Depth
64 M Samples
32 M Samples [1]
[1] With all pods assigned in transitional/store qualified timing, minimum sample period is 5 ns and maximum memory depth is 16 M samples.



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