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ST7568 Datasheet(PDF) 39 Page - Sitronix Technology Co., Ltd. |
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ST7568 Datasheet(HTML) 39 Page - Sitronix Technology Co., Ltd. |
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39 / 73 page ![]() ST7568 Ver 2.2 39/73 2008/01/04 Display Control This bits D and E selects the display mode. A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 D 0 E Flag Description D E The bits D and E select the display mode. 0 0 Display off 1 0 Normal display 0 1 All display segments on D,E 1 1 Inverse video mode Set Y address of RAM Y [3:0] defines the Y address vector address of the display RAM. A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 Y3 Y2 Y1 Y0 X/Y Address range Y3 Y2 Y1 Y0 CONTENT ALLOWED X-RANGE 0 0 0 0 Page0 (display RAM) 0 to 101 0 0 0 1 Page1 (display RAM) 0 to 101 0 0 1 0 Page2 (display RAM) 0 to 101 0 0 1 1 Page3 (display RAM) 0 to 101 0 1 0 0 Page4 (display RAM) 0 to 101 0 1 0 1 Page5 (display RAM) 0 to 101 0 1 1 0 Page6 (display RAM) 0 to 101 0 1 1 1 Page7 (display RAM) 0 to 101 1 0 0 0 Page8 (display RAM) 0 to 101 1 0 0 1 Page9 (display RAM) 0 to 101 Start line set Sets the line address of display RAM to determine the initial display line instruction. The RAM display data is displayed at the top of row (COM0) of LCD panel. A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 S5 S4 S3 S2 S1 S0 S5 S4 S3 S2 S1 S0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 1 1 3 : : : : : : : 1 1 1 1 0 0 61 1 1 1 1 0 1 62 1 1 1 1 1 0 62 1 1 1 1 1 1 63 |
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