ST7568 datasheet(22/73 Pages) SITRONIX

22 / 73 page

ST7568

Ver 2.2

22/73

2008/01/04

SEG output

SEG

…

SEG

100

SEG

101

Column

address [X6:X0]

00H

01H

02H

03H

…

62H

63H

64H

65H

Internal column

address

HEX

…

HEX

Display data

(MX=0)

…

LCD panel

display

…

Display data

(MX=1)

…

LCD panel

display

…

Figure10.The Relationship between the Column Address and The Segment Outputs

ADDRESSING

Data is downloaded in bytes into the RAM matrix of ST7568 as indicated in Figs.11, 12,13. The display RAM has a matrix

of 68 by 102 × 2 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101), Y 0 to 9

(1001). Addresses outside these ranges are not allowed.

In vertical addressing mode (V=1) the Y address increments after each byte (see Fig.13). After the last Y address (Y = 9) Y

wraps around to 0 and X increments to address the next column.

In horizontal addressing mode (V=0) the X address increments after each byte (see Fig.12). After the last X address

(X = 101) X wraps around to 0 and Y increments to address the next row.

After the very last address (X = 101, Y = 9) the address pointers wrap around to address (X = 0, Y =0)

Data structure

LSB

MSB

101

X-address

LSB

MSB

1 bit

Fig.11 RAM format, addressing

ST7568 Datasheet(PDF) 22 Page - Sitronix Technology Co., Ltd.

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