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ST7773 Datasheet(PDF) 59 Page - Sitronix Technology Co., Ltd. |
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ST7773 Datasheet(HTML) 59 Page - Sitronix Technology Co., Ltd. |
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59 / 128 page ![]() ST7773 Ver. 2.0 2008-07-07 59 9.18.2 Reset Timing VSS=0V, VDDI=1.6 to 3.3V, VDD=2.7 to 3.3V, Ta = 25 ) ℃ Symbol Parameter Related Pins MIN TYP MAX Note Unit tRESW *1) Reset low pulse width RESX 10 - - - us tREST Reset complete time - 120 - - ms Note 1 Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below. Note 2. During Reset Complete Time, ID2 and VCOMOF value in EEPROM will be latched to internal register during this period.This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX. Note 3. Spike Rejection also applies during a valid reset pulse as shown below: RESX Pulse Action Shorter than 5us Reset Rejected Longer than 10us Reset Between 5us and 10us Reset starts (It depends on voltage and temperature condition.) "RESET" is accepted 10us 10us |
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