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ST7773 Datasheet(PDF) 22 Page - Sitronix Technology Co., Ltd. |
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ST7773 Datasheet(HTML) 22 Page - Sitronix Technology Co., Ltd. |
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22 / 128 page ![]() ST7773 Ver. 2.0 2008-07-07 22 8.3 Serial interface characteristics (3-line serial) CSX VIH VIL TCHW TCSH TOH TCSS SCL SDA SDA (DOUT) TSCC TSCYCW/TSCYCR TACC VIH VIL VIH VIL VIH VIL VIH VIL TSDS TSDH TSHW/TSHR TSLW/TSLR Fig. 8.3.1 3-line serial interface timing Signal Symbol Parameter Min Max Unit Description TCSS Chip select setup time 60 ns TCSH Chip select hold time 60 ns TSCC Chip select setup time 10 ns CSX TCHW Chip select hold time 10 ns TSCYCW Serial clock cycle (Write) 65 ns TSHW SCL “H” pulse width (Write) 20 ns TSLW SCL “L” pulse width (Write) 40 ns TSCYCR Serial clock cycle (Read) 150 ns TSHR SCL “H” pulse width (Read) 60 ns SCL TSLR SCL “L” pulse width (Read) 80 ns TSDS Data setup time 10 ns TSDH Data hold time 15 ns TACC Access time 80 ns SDA (DIN) (DOUT) TOH Output disable time 45 80 ns For maximum CL=30pF Table 8.3: 3-line Serial Interface Characteristics Note 1: VDDI=1.6 to 3.3V, VDD=2.7 to 3.3V, AGND=DGND=0V, Ta=25℃ Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. |
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