LPC1766 datasheet(16/66 Pages) NXP

16 / 66 page

LPC1769_68_67_66_65_64_4

Product data sheet

Rev. 04 — 1 February 2010

16 of 66

NXP Semiconductors

LPC1769/68/67/66/65/64

32-bit ARM Cortex-M3 microcontroller

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to 8 regions each of which can be

divided into 8 subregions. Accesses to memory locations that are not defined in the MPU

regions, or not permitted by the region setting, will cause the Memory Management Fault

exception to take place.

7.6 Memory map

The LPC17xx incorporates several distinct memory regions, shown in the following

figures. Figure 3 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.

The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

LPC1766 Datasheet(PDF) 16 Page - NXP Semiconductors