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DM9010BEP Datasheet(PDF) 28 Page - Davicom Semiconductor, Inc.

Part # DM9010BEP
Description  10/100 Mbps Single Chip Ethernet Controller With General Processor Interface
PDF  62 Pages
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Manufacturer  DAVICOM [Davicom Semiconductor, Inc.]
Direct Link  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9010BEP Datasheet(HTML) 28 Page - Davicom Semiconductor, Inc.

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DM9010B
Single Chip Ethernet Controller with General Processor Interface
Preliminary
28
Version: DM9010B--DS-P01
September 5, 2007
6.37 INT Pin Control Register (39H)
Bit
Name
Default
Description
7:2
Reserved
PS0,RO
Reserved
1
INT_TYPE
PET0,RW
INT Pin Output Type Control
1: INT Open-Collector output
0: INT direct output
0
INT_POL
PET0,RW
INT Pin Polarity Control
1: INT active low
0: INT active high
6.38 Monitor Register 1 (40H)
Bit
Name
Default
Description
7
BWIDTH
T0,RO
8-bit Data Strap Latch Status
6
DWIDTH
T0,RO
32-bit Data Strap Latch Status
5
INTOC
ET0,RO
INT Open-Collect Pin Status
4
INTP
ET0,RO
INT Polarity Pin Status
3
IO16OC
E0,RO
IO16/32 Open-Collect Pin Status
2
IO16P
E0,RO
IO16/32 Polarity Pin Status
1
ILEDM
ET0,RO
LED Mode Status
0
MDIX
ET0,RO
MDIX Strap Pin Status
6.39 Monitor Register 2 (41H)
Bit
Name
Default
Description
7~4
RESERVED
0,RO
Reserved
3
NOEEP
T0,RO
NO Load EEPROM Strap Pin Status
2
EXTMII
T0,RO
External MII Strap Pin Status
1
PHYUP
T0,RO
PHY Power-Up Strap Pin Status
0
RMII
T0,RO
Reverse MII strap Pin Status
6.40 System Clock Turn ON Control Register (50H)
Bit
Name
Default
Description
7:1
Reserved
-
Reserved
0
DIS_CLK
P0,W
Stop Internal System Clock
1: internal system clock turn off, internal PHYceiver also power down
0: internal system clock is ON
6.41 Resume System Clock Control Register (51H)
When the INDEX port set to 51H, the internal system clock is turn ON.
6.42 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
7:0
MRCMDX
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged. And the DM9010B starts to pre-fetch the SRAM data
to internal data buffers.



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