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DM9010BEP Datasheet(PDF) 32 Page - Davicom Semiconductor, Inc.

Part # DM9010BEP
Description  10/100 Mbps Single Chip Ethernet Controller With General Processor Interface
PDF  62 Pages
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Manufacturer  DAVICOM [Davicom Semiconductor, Inc.]
Direct Link  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9010BEP Datasheet(HTML) 32 Page - Davicom Semiconductor, Inc.

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DM9010B
Single Chip Ethernet Controller with General Processor Interface
Preliminary
32
Version: DM9010B--DS-P01
September 5, 2007
8. MII REGISTER DESCRIPTION
ADD
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
Loop
back
Speed
select
Auto-N
Enable
Power
Down
Isolate
Restart
Auto-N
Full
Duplex
Coll.
Test
Reserved
00
CONTR
OL
0
0
1
1
0
0
0
1
0
000_0000
T4
Cap.
TX FDX
Cap.
TX HDX
Cap.
10 FDX
Cap.
10 HDX
Cap.
Reserved
Pream.
Supr.
Auto-N
Compl.
Remote
Fault
Auto-N
Cap.
Link
Status
Jabber
Detect
Extd
Cap.
01 STATUS
0
1
1
1
1
0000
1
0
0
1
0
0
1
02
PHYID1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
OUI_LSB
Model No.
Version No.
03
PHYID2
101110
01010
0000
04 Auto-Neg.
Advertise
Next
Page
FLP Rcv
Ack
Remote
Fault
Reserved
FC
Adv
T4
Adv
TX FDX
Adv
TX HDX
Adv
10 FDX
Adv
10 HDX
Adv
Advertised Protocol Selector Field
05 Link Part.
Ability
LP
Next
Page
LP
Ack
LP
RF
Reserved
LP
FC
LP
T4
LP
TX FDX
LP
TX HDX
LP
10 FDX
LP
10 HDX
Link Partner Protocol Selector Field
06 Auto-Neg.
Expansio
n
Reserved
Pardet
Fault
LP Next
Pg Able
Next Pg
Able
New Pg
Rcv
LP AutoN
Cap.
16 Specifie
d
Config.
BP
4B5B
BP
SCR
BP
ALIGN
BP_ADP
OK
Reserve
dr
TX
Reserve
d
Reserve
d
Force
100LNK
Reserve
d
Reserve
d
RPDCTR
-EN
Reset
St. Mch
Pream.
Supr.
Sleep
mode
Remote
LoopOut
17 Specifie
d
Conf/Stat
100
FDX
100
HDX
10
FDX
10 HDX Reserve
d
Reverse
d
Reverse
d
PHY ADDR [4:0]
Auto-N. Monitor Bit [3:0]
18
10T
Conf/Stat
Rsvd
LP
Enable
HBE
Enable
SQUE
Enable
JAB
Enable
Reserve
d
Reserved
Polarity
Reverse
19
PWDOR
Reserved
PD10DR
V
PD100l
PDchip
PDcrm
PDaeq
PDdrv
PDecli
PDeclo
PD10
20
Specified
config
TSTSE1 TSTSE2 FORCE_
TXSD
FORCE_
FEF
Reserved
MDIX_C
NTL
AutoNeg
_dlpbk
Mdix_fix
Value
Mdix_do
wn
MonSel1 MonSel0 Reserve
d
PD_valu
e
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high



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