STM32F100C6 datasheet(68/84 Pages) STMICROELECTRONICS

68 / 84 page

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

68/84

Doc ID 16455 Rev 2

negative currents.

Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in

Section 5.3.12 does not affect the ADC accuracy.

Figure 31.

ADC accuracy characteristics

Figure 32.

Typical connection diagram using the ADC

Refer to Table 41 for the values of RAIN, RADC and CADC.

Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy

this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 33 or Figure 34,

depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be

ceramic (good quality). They should be placed them as close as possible to the chip.

1LSBIDEAL

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

ET=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

EO=Offset Error: deviation between the first actual

transition and the first ideal one.

EG=Gain Error: deviation between the last ideal

transition and the last actual one.

ED=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

EL=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

4095

4094

4093

456

4093 4094 4095 4096

(1)

(2)

(3)

VDDA

VSSA

ai14395b

VREF+

4096

(or

depending on package)]

VDDA

4096

[1LSBIDEAL =

ai14139d

STM32F10xxx

VDD

AINx

IL±1 µA

0.6 V

RAIN(1)

Cparasitic

VAIN

0.6 V

RADC(1)

CADC(1)

12-bit

converter

Sample and hold ADC

converter

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