74ABT821_3

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Product data sheet

Rev. 03 — 25 February 2010

7 of 16

NXP Semiconductors

74ABT821

10-bit D-type flip-flop; positive-edge trigger; 3-state

10. Dynamic characteristics

11. Waveforms

Table 7.

Dynamic characteristics

GND = 0 V; for test circuit, see Figure 8.

Symbol Parameter

Conditions

25

°C; V

−40 °C to +70 °C;

Unit

Min

Typ

Max

Min

Max

LOW to HIGH

propagation delay

CP to Qn; see Figure 5

2.1

4.1

5.6

2.1

6.2

ns

HIGH to LOW

propagation delay

CP to Qn; see Figure 5

2.8

4.6

6.2

2.8

6.7

ns

OFF-state to HIGH

propagation delay

OEn to Qn; see Figure 6

1.0

3.0

4.5

1.0

5.3

ns

OFF-state to LOW

propagation delay

OEn to Qn; see Figure 6

2.2

4.1

5.6

2.2

6.3

ns

HIGH to OFF-state

propagation delay

OEn to Qn; see Figure 6

2.7

4.7

6.2

2.7

6.7

ns

LOW to OFF-state

propagation delay

OEn to Qn; see Figure 6

2.3

4.6

6.1

2.3

6.5

ns

set-up time HIGH

Dn to CP; see Figure 7

2.1

0.5

-

2.1

-

ns

set-up time LOW

Dn to CP; see Figure 7

2.1

0.3

-

2.1

-

ns

hold time HIGH

Dn to CP; see Figure 7

1.3

0

-

1.3

-

ns

hold time LOW

Dn to CP; see Figure 7

1.3

−0.3

-

1.3

-

ns

pulse width HIGH

CP; see Figure 5

2.9

1.8

-

2.9

-

ns

pulse width LOW

CP; see Figure 5

3.8

2.8

-

3.8

-

ns

maximum

frequency

see Figure 5

125

185

-

125

-

MHz

Fig 5.

Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and

maximum clock (CP) frequency

001aac445

CP input

Qn output

GND