1.

General description

The 74ABT821 high-performance BiCMOS device combines low static and dynamic

power dissipation with high speed and high output drive.

The 74ABT821 bus interface register is designed to eliminate the extra packages required

to buffer existing registers and provide extra data width for wider data/address paths of

buses carrying parity.

The 74ABT821 is a buffered 10-bit wide version of the 74ABT374A.

The 74ABT821 is a 10-bit, edge-triggered register coupled to ten 3-state output buffers.

The device is controlled by the clock (CP) and output enable (OE) control gates.

The register is fully edge triggered. The state of each D input, one set-up time before the

LOW-to-HIGH clock transition is transferred to the corresponding output Q of the flip-flop.

The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS

memories, or MOS microprocessors.

The active LOW output enable (OE) controls all ten 3-state buffers independent of the

register operation. When OE is LOW, the data in the register appears at the outputs.

When OE is HIGH, the outputs are in high-impedance OFF-state, which means they will

neither drive nor load the bus.

2.

Features and benefits

microprocessors

74ABT821

10-bit D-type flip-flop; positive-edge trigger; 3-state

Rev. 03 — 25 February 2010

Product data sheet