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ICS9EX21801A Datasheet(PDF) 2 Page - Integrated Device Technology |
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ICS9EX21801A Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 14 page ![]() IDTTM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463B — 01/20/10 ICS9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 2 Datasheet Pin Configuration 72-pin MLF Power Down Functionality Power Groups 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDD 1 54 DIF_6# OE10# 2 53 DIF_6 DIF_10 3 52 OE6# DIF_10# 4 51 DIF_5# OE11# 5 50 DIF_5 DIF_11 6 49 OE5# DIF_11# 7 48 DIF_4# OE12# 8 47 DIF_4 DIF_12 9 46 DIF_3# DIF_12# 10 45 DIF_3 GND 11 44 GND VDD 12 43 VDD DIF_13 13 42 DIF_2# DIF_13# 14 41 DIF_2 OE13# 15 40 DIF_1# DIF_14 16 39 DIF_1 DIF_14# 17 38 DIF_0# OE14# 18 37 DIF_0 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 9EX21801AKLF VDD GND 29 28 Main PLL, Analog 1,12,21,35,43,55 11,32,44 DIF clocks Description Pin Number OUTPUTS CKPWRGD/PD# Input DIF_x 1 Running Running ON 0X Hi-Z OFF PLL State INPUTS SMBus Address Selection (pins 66, 67) HIBW_BYPM_LOBW# Selection (Pin 63) State Voltage Mode Low <0.8V Low BW Mid 1.2<Vin<1.8V Bypass High Vin > 2.0V High BW SMB_A1 SMB_A0 Address 00 D4 01 D6 10 D8 11 DA Byte 0, bit 2 (100_133M# Latch) Byte 0, bit 1 FSB Byte 0, bit 0 FSA Input MHz DIF_x MHz Notes 1 01 100.00 100.00 1 0 01 133.33 133.33 1 01 1 166.67 166.67 2 01 0 200.00 200.00 2 00 0 266.67 266.67 2 10 0 333.33 333.33 2 11 0 400.00 400.00 2 11 1 Notes:100M_133M# 1. Latch selects between 100 and 133 MHz. This is equivalent to FSC in CK410B+/CK509B FS table. 2. Writing Byte 0 bits (2:0) can select other frequencies. These frequencies are not characterized in PLL Mode Frequency/Functionality Table Reserved |
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