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TPS62619YFD Datasheet(PDF) 19 Page - Texas Instruments |
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TPS62619YFD Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 27 page ![]() TPS62619, TPS62612 TPS62615, TPS62616 www.ti.com SLVS936A – NOVEMBER 2009 – REVISED MARCH 2010 OUTPUT CAPACITOR SELECTION The advanced fast-response voltage mode control scheme of the TPS6261x allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. For best performance, the device should be operated with a minimum effective output capacitance of 1.6mF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor impedance. At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load transitions. A 4.7mF capacitor typically provides sufficient bulk capacitance to stabilize the output during large load transitions. The typical output voltage ripple is 1% of the nominal output voltage VO. The output voltage ripple during PFM mode operation can be kept very small. The PFM pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. The PFM frequency decreases with smaller inductor values and increases with larger once. Increasing the output capacitor value and the effective inductance will minimize the output ripple voltage. INPUT CAPACITOR SELECTION Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interferences with other circuits in the system. For most applications, a 2.2-mF capacitor is sufficient. If the application exhibits a noisy or erratic switching frequency, the remedy will probably be found by experimenting with the value of the input capacitor. Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed between CI and the power source lead to reduce ringing than can occur between the inductance of the power source leads and CI. CHECKING LOOP STABILITY The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: • Switching node, SW • Inductor current, IL • Output ripple voltage, VO(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination. As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error signal used by the regulator to return VO to its steady-state value. The results are most easily interpreted when the device operates in PWM mode. During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range, and temperature range. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link(s): TPS62619 TPS62612 TPS62615 TPS62616 |
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