WM8731 datasheet(4/56 Pages) WOLFSON

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WM8731

Advanced Information

WOLFSON MICROELECTRONICS LTD

AI Rev 2.0 February 2001

TABLE OF FIGURES

Figure 1 System Clock Timing Requirements ............................................................................ 12

Figure 2 Clock Out Timing Requirements................................................................................... 12

Figure 3 Master Mode Connection .............................................................................................. 13

Figure 4 Digital Audio Data Timing – Master Mode ................................................................... 13

Figure 5 Slave Mode Connection.................................................................................................14

Figure 6 Digital Audio Data Timing – Slave Mode...................................................................... 14

Figure 7 Program Register Input Timing - 3-Wire MPU Serial Control Mode .......................... 15

Figure 8 Program Register Input Timing – 2-Wire MPU Serial Control Mode ......................... 16

Figure 9 Line Input Schematic ..................................................................................................... 18

Figure 10 Line Input Application Drawing .................................................................................. 19

Figure 11 Microphone Input Schematic ...................................................................................... 20

Figure 12 Microphone Input and Bias Application Drawing ..................................................... 21

Figure 13 Microphone Bias Schematic ....................................................................................... 22

Figure 14 Multi-Bit Oversampling Sigma Delta ADC Schematic............................................... 22

Figure 15 ADC Digital Filter .......................................................................................................... 23

Figure 16 DAC Filter Schematic ................................................................................................... 23

Figure 17 Multi-Bit Oversampling Sigma Delta Schematic ....................................................... 24

Figure 18 Line Output Schematic ................................................................................................25

Figure 19 Line Outputs Application Drawing ............................................................................. 26

Figure 20 Headphone Amplifier Schematic ................................................................................ 26

Figure 21 Headphone Output Application Drawing ................................................................... 28

Figure 22 Signal Routing in Bypass Mode................................................................................... 28

Figure 23 Side Tone Mode Schematic......................................................................................... 29

Figure 24 Crystal Oscillator Application Circuit.......................................................................... 31

Figure 25 Left Justified Mode........................................................................................................ 32

Figure 26 I2S Mode........................................................................................................................ 33

Figure 27 Right Justified Mode ..................................................................................................... 33

Figure 28 DSP Mode....................................................................................................................... 33

Figure 29 Master Mode ................................................................................................................. 36

Figure 30 Slave Mode..................................................................................................................... 36

Figure 31 3-Wire Serial Interface................................................................................................... 42

Figure 32 2-Wire Serial Interface.................................................................................................. 42

Figure 33 DAC Digital Filter Frequency Response –Type 0 ....................................................... 51

Figure 34 DAC Digital Filter Ripple –Type 0................................................................................. 51

Figure 35 DAC Digital Filter Frequency Response –Type 1 ....................................................... 51

Figure 36 DAC Digital Filter Ripple –Type 1................................................................................. 51

Figure 37 DAC Digital Filter Frequency Response –Type 2 ....................................................... 51

Figure 38 DAC Digital Filter Ripple –Type 2................................................................................. 51

Figure 39 DAC Digital Filter Frequency Response –Type 3 ....................................................... 52

Figure 40 DAC Digital Filter Ripple –Type 3................................................................................. 52

Figure 41 ADC Digital Filter Frequency Response –Type 0 ....................................................... 52

Figure 42 ADC Digital Filter Ripple –Type 0................................................................................. 52

Figure 43 ADC Digital Filter Frequency Response –Type 1 ....................................................... 52

Figure 44 ADC Digital Filter Ripple –Type 1................................................................................. 52

Figure 45 ADC Digital Filter Frequency Response –Type 2 ....................................................... 53

Figure 46 ADC Digital Filter Ripple –Type 2................................................................................. 53

Figure 47 ADC Digital Filter Frequency Response –Type 3 ....................................................... 53

Figure 48 ADC Digital Filter Ripple –Type 3................................................................................. 53

Figure 49 De-Emphasis Frequency Response (32kHz) .............................................................. 54

Figure 50 De-Emphasis Error (32kHz) .......................................................................................... 54

Figure 51 De-Emphasis Frequency Response (44.1kHz) ........................................................... 54

Figure 52 De-Emphasis Error (44.1kHz) ....................................................................................... 54

Figure 53 De-Emphasis Frequency Response (48kHz) .............................................................. 54

Figure 54 De-Emphasis Error (48kHz) .......................................................................................... 54

Figure 55 External Components Diagram.................................................................................... 55

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