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APPLICATION INFORMATION (cont.)

SS8000G

External Components Selection

Input Capacitor Selection

For each of the input pins (VBAT) of the SS8000, a

10µF, low ESR capacitor is recommended for local by-

pass. MLCC capacitors provide the best combination of

low ESR and small size. Using a 10µF tantalum capaci-

tor with a small (1µF or 2.2µF) ceramic in parallel is an

alternative low cost solution.

For the charger input pin (CHRIN), a 1µF ceramic ca-

pacitor is recommended for bypass.

LDO Capacitor Selection

The digital core, analog, and memory LDOs require a

4.7µF capacitor, the digital IO and SIM TCXO LDOs

require a 1µF capacitor and the RTC LDO requires a

0.22µF capacitor. Larger value capacitors may be used

for improved noise or PSRR performance, but do not

forget to consider the settling time that is acceptable for

the application. For these, MLCC is recommended.

RESET Capacitor Selection

RESET is held low during power-up for a delay until the

LDOs are up. The delay is set by an external capacitor

on the RESCAP pin. It can be determined by Eq.(1). A

100nF capacitor will produce a 200ms delay.

Setting the Charge Current

The SS8000 is capable of charging the battery with a

charging current programmed by an external sense re-

sistor, Rsen. It is calculated using Eq.(3). If the charge

current is defined, Rsen can be found.

Appropriate sense resistors are available from the fol-

lowing vendors: Vishay Dale, IRC, Panasonic.

Charger FET Selection

In selecting the P-channel MOSFET for the charger,

consider the minimum drain-source breakdown voltage

(BVDS), the minimum turn-on threshold voltage (VGS),

and current-handling and power-dissipation capabilities.

Charger Diode Selection

The diode shown in Figure 3 is used to prevent the bat-

tery from discharging through the P-channel MOSFETs

body-diode into the charger’s internal circuits. Choose a

diode with a current rating high enough to handle the

battery charging current and a voltage rating greater

than Vbat.

Layout Guidelines

Use the following general guidelines when designing the

printed circuit boards:

1. Split the battery connection to the VBAT, AVBAT pins

of the SS8000. Locate the input capacitor as close

to the pins as possible.

2. Va and Vtcxo capacitors should be returned to AGND.

3. Split the ground connection. Use separate traces or

planes for the analog, digital, and power grounds (i.e.

AGND, DGND, PGND pins of the SS8000, respec-

tively) and tie them together at a single point, prefera-

bly close to the battery return.

4. Run a separate trace from the BATSNS pin to the

battery to prevent any voltage drop error in the meas-

urement.

5. Kelvin-connect the charge-current sense-resistor by

running separate traces to the BATSNS and ISENSE

pins. Make sure that the traces are terminated as

close to the resistor’s body as possible.

6. Careful use of copper area, weight, and multi-layer

construction will help to improve thermal performance.

12/06/2004 Rev.2.10