X68C75PI datasheet(4/26 Pages) XICOR

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X68C75 SLIC® E2

determine the early completion of a write cycle. During

the internal programming cycle, I/O6 will toggle from “1”

to “0” and “0” to “1” on subsequent attempts to read from

the memory plane that is being updated. When the

internal cycle is complete, the toggling will cease and the

device will be accessible for additional read or write

operations. Due to the dual plane architecture, reads for

polling must occur from the plane that was written; that

is, the state of A12 during a write must match the state of

A12 during polling.

DATA PROTECTION

The X68C75 provides two levels of data protection

through software control. There is a global software data

protection feature similar to the industry standard for

E2PROMs and a new Block Lock Protect write lockout

protection providing a secondary level data security

option.

Figure 1. Toggle Bit Polling E Control

A/D0–A/D7

A8–A12

R/W

AIN

DIN

A12=n

OPERATION

LAST BYTE

WRITTEN

I/O6=X

X68C75 READY FOR

NEXT OPERATION

2899 ILL F05

AIN DOUT

A12=n

AIN DOUT

A12=n

AIN DOUT

A12=n

AIN

A12=n

AIN

ADDR

I/O6=X

DOUT

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