X68C75PI datasheet(5/26 Pages) XICOR

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X68C75 SLIC® E2

Software Data Protection

Software Data Protection (SDP) can be employed to

protect the entire array against inadvertent writes during

power-up/power-down operations. The X68C75 is

shipped from the factory with SDP enabled. With SDP

enabled, inadvertent attempts to write to the X68C75 will

be blocked.

The system can still write data, but only when the write

operation (page or byte) is preceded by the three-byte

command sequence. All write operations, both the com-

mand sequence and any data write operations must

conform to the page write timing requirements.

The SDP mode is also enabled anytime one of the

nonvolatile configuration registers are modified. These

include writing to EE map, SFR map, and BPR.

Block Lock Protect Write Lockout

The X68C75 provides a second level of data security

referred to as Block Lock Protect write lockout (or Block

Protection). This is accessed through an extension of

the SDP command sequence. Block Protect allows the

user to lockout writes to 1K x 8 blocks of memory. Unlike

SDP which prevents inadvertent writes, but still allows

easy system access to writing the memory, Block Pro-

tect will lockout all attempts unless it is specifically

disabled by issuing the deactivation sequence. This

feature can be used to set a higher level of protection in

a system where a portion of the memory is used to store

the system kernel and protect it from the application

programs residing in the other blocks.

Setting write lockout is accomplished by writing a five-

byte command sequence opening access to the Block

Protect Register (BPR). After the fifth byte is written, the

user writes to the BPR, selecting which blocks to protect

or unprotect. All write operations, both the command

sequence and writing the data to the BPR, must conform

to the page write timing requirements. It should be noted

that accessing the BPR automatically sets the upper

level SDP. If for some reason the user does not want

SDP enabled, they may reset it using the normal reset

command sequence. This will

not affect the state of the

BPR and any 1K x 8 blocks that were set to the write

lockout state will remain in the write lockout state.

P 555

b1 b0

AAA

b1 b0

P 555

b1 b0

2899 ILL F05C

Reference the A15–A13

setting in EEM register

Delay of tWC

Exit Routine

P = Address bit (A12) of the

memory plane not being read.

b2 b1 b0

P 555

b1 b0

P AAA

b1 b0

Figure 3. Sequence to Deactivate

Software Data Protection

P 555

b1 b0

AAA

b1 b0

P 555

b1 b0

2899 ILL F05B

Perform Byte or Page

Write Operations

Reference the A15–A13

setting in EEM register

Delay of tWC

Exit Routine

P = Address bit (A12) of the

updated memory plane.

b2 b1 b0

Figure 2. Writing with SDP Enabled

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