16-Bit Microcontroller with Infrared Module

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Operating Modes

The lowest power mode of operation is stop mode. In this

mode, CPU state and memories are preserved, but the

CPU is not actively running. Wake-up sources include

external I/O interrupts, the power-fail warning interrupt,

wake-up timer, or a power-fail reset. Any time the micro-

controller is in a state where code does not need to be

executed, the user software can put the device into stop

mode. The nanopower ring oscillator is an internal ultra-

low-power (400nA) 8kHz ring oscillator that can be used

to drive a wake-up timer that exits stop mode. The wake-

up timer is programmable by software in steps of 125Fs

up to approximately 8s.

The power-fail monitor is always on during normal opera-

tion. However, it can be selectively disabled during stop

mode to minimize power consumption. This feature is

enabled using the power-fail monitor disable (PFD) bit

in the PWCN register. The reset default state for the PFD

bit is 1, which disables the power-fail monitor function

during stop mode. If power-fail monitoring is disabled

(PFD = 1) during stop mode, the circuitry responsible

for generating a power-fail warning or reset is shut down

condition does not invoke a reset state.

Power-Fail Detection

Figures 10, 11, and 12 show the power-fail detection and

response during normal and stop-mode operation. If a

reset is caused by a power-fail, the power-fail monitor

can be set to one of the following intervals:

• Always on—continuous monitoring

In the case where the power-fail circuitry is periodically

turned on, the power-fail detection is turned on for two

the third nanopower ring period, the CPU exits the reset

state and resumes normal operation from utility ROM at

8000h after satisfying the crystal warmup period.

If a reset is generated by any other event, such as the

RESET pin being driven low externally or the watchdog

timer, the power-fail, internal regulator, and crystal

remain on during the CPU reset. In these cases, the CPU

exits the reset state in less than 20 crystal cycles after

the reset source is removed.

Figure 10. Power-Fail Detection During Normal Operation

A

B

C

D

F

G

H

I

E

INTERNAL RESET

(ACTIVE HIGH)

t

t

t

t