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AM1707 Datasheet(PDF) 144 Page - Texas Instruments |
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AM1707 Datasheet(HTML) 144 Page - Texas Instruments |
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144 / 198 page  AM1707 SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010 www.ti.com 6.22.2 LCD Raster Mode Table 6-84. LCD Raster Mode Timing See Figure 6-55 through Figure 6-59 No. PARAMETER MIN MAX UNIT 1 tc(PIXEL_CLK) Cycle time, pixel clock 26.6 ns 2 tw(PIXEL_CLK_H) Pulse duration, pixel clock high 10 ns 3 tw(PIXEL_CLK_L) Pulse duration, pixel clock low 10 ns 4 td(LCD_D_V) Delay time, LCD_PCLK ↑ to LCD_D[15:0] valid (write) 0 12 ns 5 td(LCD_D_IV) Delay time, LCD_PCLK ↑ to LCD_D[15:0] invalid (write) 0 12 ns 6 td( LCD_AC_ENB_CS_A ) Delay time, LCD_PCLK ↓ to LCD_AC_ENB_CS↑ S2 + 0 (1) S2 + 12 (1) ns 7 td( LCD_AC_ENB_CS_I) Delay time, LCD_PCLK ↓ to LCD_AC_ENB_CS↓ S2 + 0 (1) S2 + 12 (1) ns 8 td(LCD_VSYNC_A) Delay time, LCD_PCLK ↓ to LCD_VSYNC↑ 0 12 ns 9 td(LCD_VSYNC_I) Delay time, LCD_PCLK ↓ to LCD_VSYNC↓ 0 12 ns 10 td(LCD_HSYNC_A) Delay time, LCD_PCLK ↑ to LCD_HSYNC↑ 0 12 ns 11 td(LCD_HSYNC_I) Delay time, LCD_PCLK ↑ to LCD_HSYNC↓ 0 12 ns (1) S2 = SYSCLK2 cycle time in ns Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1) register: • Vertical front porch (VFP) • Vertical sync pulse width (VSW) • Vertical back porch (VBP) • Lines per panel (LPP) Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register: • Horizontal front porch (HFP) • Horizontal sync pulse width (HSW) • Horizontal back porch (HBP) • Pixels per panel (PPL) LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2) register: • AC bias frequency (ACB) The display format produced in raster mode is shown in Figure 6-55. An entire frame is delivered one line at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the activation of I/O signal LCD_HSYNC. 144 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 |
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