1.

General description

The 74HC73 is a high-speed Si-gate CMOS device that complies with JEDEC

standard no. 7A. It is pin compatible with Low-power Schottky TTL (LSTTL).

The 74HC73 is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock

(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.

The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock

transition for predictable operation.

The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock

and data inputs, forcing the nQ output LOW and the nQ output HIGH.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock

rise and fall times.

2.

Features

3.

Ordering information

74HC73

Dual JK flip-flop with reset; negative-edge trigger

Rev. 04 — 19 March 2008

Product data sheet

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC73N

−40 °C to +125 °C

DIP14

plastic dual in-line package; 14 leads (300 mil)

SOT27-1

74HC73D

−40 °C to +125 °C

SO14

plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

74HC73DB

−40 °C to +125 °C

SSOP14

plastic shrink small outline package; 14 leads; body width

5.3 mm

SOT337-1

74HC73PW

−40 °C to +125 °C

TSSOP14 plastic thin shrink small outline package; 14 leads; body

width 4.4 mm

SOT402-1