AM1707BZKB4 datasheet(29/155 Pages) TI

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AM1705

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SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010

Device Configuration

4.1

Boot Modes

This device supports a variety of boot modes through an internal ROM bootloader. This device does not

support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input

states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system

configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by

the values of the BOOT pins

The following boot modes are supported:

•

NAND Flash boot

–

8-bit NAND

•

NOR Flash boot

–

NOR Direct boot (8-bit or 16-bit)

–

NOR Legacy boot (8-bit or 16-bit)

–

NOR AIS boot (8-bit or 16-bit)

•

I2C0 / I2C1 Boot

–

EEPROM (Master Mode)

–

External Host (Slave Mode)

•

SPI0 / SPI1 Boot

–

Serial Flash (Master Mode)

–

SERIAL EEPROM (Master Mode)

–

External Host (Slave Mode)

•

UART0 / UART1 / UART2 Boot

–

External Host

4.2

SYSCFG Module

The following system level features of the chip are controlled by the SYSCFG peripheral:

•

Readable Device, Die, and Chip Revision ID

•

Control of Pin Multiplexing

•

Priority of bus accesses different bus masters in the system

•

Capture at power on reset the chip BOOT[15:0] pin values and make them available to software

•

Special case settings for peripherals:

–

Locking of PLL controller settings

–

Default burst sizes for EDMA3 TC0 and TC1

–

Selection of the source for the eCAP module input capture (including on chip sources)

–

McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals

–

Control of the reference clock source and other side-band signals for both of the integrated USB

PHYs

–

Clock source selection for EMIFA and EMIFB

•

Selects the source of emulation suspend signal of peripherals supporting this function.

Since the SYSCFG peripheral controls global operation of the device, its registers are protected against

erroneous accesses by several mechanisms:

•

A special key sequence must be written to KICK0, KICK1 registers before any other registers are

writeable.

•

Additionally, many registers are accessible only by a host (ARM) when it is operating in its privileged

mode. (ex. from the kernel, but not from user space code).

Device Configuration

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