ADC1015S datasheet(21/39 Pages) NXP

Part #	ADC1015S

Description	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Preliminary data sheet

PDF	39 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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21 / 39 page

ADC1015S_SER_1

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Preliminary data sheet

Rev. 01 — 12 April 2010

21 of 39

NXP Semiconductors

ADC1015S series

ADC1015S series; input buffer; CMOS or LVDS DDR digital output

11.4 Clock input

11.4.1 Drive modes

The ADC1015S can be driven differentially (SINE, LVPECL or LVDS) with little or no

degradation on dynamic performances. It can also be driven by a single-ended LVCMOS

signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or

CLKM (CLKP should be connected to ground via a capacitor).

a. Rising edge LVCMOS

b. Falling edge LVCMOS

Fig 16. LVCMOS single-ended clock input

a. Sine clock input

b. Sine clock input (with transformer)

c. LVDS clock input

d. LVPECL clock input

Fig 17. Differential clock input

LVCMOS

clock input

CLKP

CLKM

005aaa174

005aaa053

LVCMOS

clock input

CLKP

CLKM

Sine

clock input

CLKP

CLKM

005aaa173

Sine

clock input

CLKP

CLKM

005aaa054

005aaa055

LVDS

clock input

CLKP

CLKM

LVPECL

clock input

005aaa172

CLKP

CLKM

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