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ADC1015S Datasheet(PDF) 13 Page - NXP Semiconductors |
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ADC1015S Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 39 page ![]() xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx [1] Typical values measured at VDDA(3V) =3 V, VDDO = 1.8 V, VDDA(5V) =5V; Tamb =25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) =3 V, VDDO =1.8 V, VDDA(5V) =5V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. [2] Measured between 20 % to 80 % of VDDO. [3] Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV. LVDS DDR mode timing output: pins D9P to D0P, D9M to D0M, DAVP and DAVM tPD propagation delay DATA -3.9 --3.9 -- 3.9 --3.9 -ns DAV - 4.2 --4.2 -- 4.2 --4.2 -ns tsu set-up time -5.1 --3.5 -- 2.1 --1.4 -ns th hold time -2.0 --2.0 -- 2.0 --2.0 -ns tr rise time[3] DATA 50 100 200 50 100 200 50 100 200 50 100 200 ps DAV 50 100 200 50 100 200 50 100 200 50 100 200 ps tf fall time[3] DATA 50 100 200 50 100 200 50 100 200 50 100 200 ps Table 8. Clock and digital output timing characteristics[1] …continued Symbol Parameter Conditions ADC1015S065 ADC1015S080 ADC1015S105 ADC1015S125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max |
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