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CS5361 Datasheet(PDF) 11 Page - Cirrus Logic

Part # CS5361
Description  114 dB, 192 kHz, Multi-Bit Audio A/D Converter
PDF  23 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5361 Datasheet(HTML) 11 Page - Cirrus Logic

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CS5361
DS467F2
11
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic “0” = GND = 0 V; Logic “1” = VL, CL = 20 pF
Parameter
Symbol
Min
Typ
Max
Unit
Output Sample Rate
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
2
50
100
-
-
-
51
102
204
kHz
kHz
kHz
OVFL to LRCK edge setup time
tsetup
16/fsclk
--
s
OVFL to LRCK edge hold time
thold
1/fsclk
--
s
OVFL time-out on overrange condition
Fs = 44.1, 88.2, 176.4 kHz
Fs = 48, 96, 192 kHz
-
-
740
680
-
-
ms
ms
MCLK Specifications
MCLK Period
tclkw
38
-
1953
ns
MCLK Pulse Duty Cycle
40
50
60
%
Master Mode
SCLK falling to LRCK
tmslr
-20
-
20
ns
SCLK falling to SDOUT valid
tsdo
0
-
32
ns
SCLK Duty Cycle
-
50
-
%
Slave Mode
Single Speed
Output Sample Rate
Fs
2
-
51
kHz
LRCK Duty Cycle
40
50
60
%
SCLK Period
tsclkw
153
-
-
ns
SCLK Duty Cycle
45
50
55
%
SCLK falling to SDOUT valid
tdss
-
-
32
ns
SCLK falling to LRCK edge
tslrd
-20
-
20
ns
Double Speed
Output Sample Rate
Fs
50
-
102
kHz
LRCK Duty Cycle
40
50
60
%
SCLK Period
tsclkw
153
-
-
ns
SCLK Duty Cycle
45
50
55
%
SCLK falling to SDOUT valid
tdss
-
-
32
ns
SCLK falling to LRCK edge
tslrd
-20
-
20
ns
Quad Speed
Output Sample Rate
Fs
100
-
204
kHz
LRCK Duty Cycle
40
50
60
%
SCLK Period
tsclkw
77
-
-
ns
SCLK Duty Cycle
45
50
55
%
SCLK falling to SDOUT valid
tdss
-
-
32
ns
SCLK falling to LRCK edge
tslrd
-8
-
3
ns



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