CS5361

18

DS467F2

4.3

Power-up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and config-

uration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the

minimum specified operating voltages to prevent power glitch related issues.

The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay be-

tween the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the

presence of the external capacitance.

4.4

Analog Connections

The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the

filter. However, there is no rejection for input signals which are (n

where n=0,1,2,...Refer to Figure 24 which shows the suggested filter that will attenuate any noise energy at

6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which

have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal

linearity.

Figure 24. CS5361 Recommended Analog Input Buffer

VQ

+

634

Ω

634

Ω

91

Ω

91

Ω

+

-

-

2700 pF

470 pF

470 pF

COG

COG

10 uF

10 uF

ADC AIN+

ADC AIN-

AIN+

AIN-

COG

100 k

Ω

10 k

Ω

10 k

Ω

100 k

Ω