CS5461 datasheet(12/45 Pages) CIRRUS

12 / 45 page

CS5461

DS546F2

SWITCHING CHARACTERISTICS

Notes: 10. Device parameters are specified with a 4.096 MHz clock. If a crystal is used, then XIN frequency must

remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used, full XIN frequency range is

2.5MHz - 20MHz.

11. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec.

12. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

13. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

3.1 Theory of Operation

A computational flow diagram for the two data

paths is shown in Fig. 2. The analog waveforms at

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

Internal Gate Oscillator (Note 10)

MCLK

2.5

4.096

MHz

Master Clock Duty Cycle

CPUCLK Duty Cycle

(Note 11)

Rise Times

Any Digital Input Except SCLK

(Note 12)

SCLK

Any Digital Output

trise

1.0

100

µs

Fall Times

Any Digital Input Except SCLK

(Note 12)

SCLK

Any Digital Output

tfall

1.0

100

µs

Start-up

Oscillator Start-Up Time

XTAL = 4.096 MHz (Note 13)

tost

-60-

Serial Port Timing

Serial Clock Frequency

SCLK

MHz

Serial Clock

Pulse Width High

Pulse Width Low

200

SDI Timing

CS Falling to SCLK Rising

Data Set-up Time Prior to SCLK Rising

Data Hold Time After SCLK Rising

100

SDO Timing

CS Falling to SDI Driving

-20

SCLK Falling to New Data Bit (hold time)

-20

CS Rising to SDO Hi-Z

-20

Auto-Boot Timing

Serial Clock

Pulse Width High

Pulse Width Low

t10

t11

MCLK

MODE setup time to RESET Rising

t12

RESET rising to CS falling

t13

MCLK

CS falling to SCLK rising

t14

100

MCLK

SCLK falling to CS rising

t15

MCLK

CS rising to driving MODE low (to end auto-boot sequence).

t16

SDO guaranteed setup time to SCLK rising

t17

100

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