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CS5461 Datasheet(PDF) 30 Page - Cirrus Logic |
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CS5461 Datasheet(HTML) 30 Page - Cirrus Logic |
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30 / 45 page  CS5461 30 DS546F2 6.1.7 Register Read/Write The Read/Write informs the state machine that a register access is required. During a read operation, the addressed register is loaded into the device’s output buffer and clocked out by SCLK. During a write operation, the data is clocked into the input buffer and, and all 24 bits are transferred to the addressed register on the 24th SCLK. W/R Write/Read control 0 = Read register 1 = Write register RA[4:0] Register address bits (bits 1 through 5) of the read/write command. Address RA[4-0] Abbreviation Name/Description 0 00000 Config Configuration Register 1 00001 IDCoff Current Offset Register 2 00010 Ign Current Gain Register 3 00011 VDCoff Voltage Offset Register 4 00100 Vgn Voltage Gain Register 5 00101 Cycle Count Number of A/D conversions used in one computation cycle (N)). 6 00110 PulseRateE Sets the EOUT/EDIR energy-to-frequency output pulse rate. 7 00111 I Instantaneous Current Register (last current value) 8 01000 V Instantaneous Voltage Register (last voltage value) 9 01001 P Instantaneous Power Register (Last Power value) 10 01010 PAvg Average Power Register (avg. power over last computation cycle) 11 01011 IRMS RMS Current Register (RMS value over last comp. cycle) 12 01100 VRMS RMS Voltage Register (RMS value over last comp. cycle) 13 01101 TBC Timebase Calibration Register 14 01110 Poff Power Offset Calibration Register 15 01111 Status Status Register (Write of ‘1’ to status bit will clear the bit.) 16 10000 IACoff AC (RMS) Current Offset Register 17 10001 VACoff AC (RMS) Voltage Offset Register 18 10010 PulseRateF Sets the FOUT power-to-frequency output pulse rate. 19 10011 T Temperature Register 20 10100 Res Reserved † 21 10101 PW Pulse width register for mechanical counter output mode 22 10110 Res Reserved † 23 10111 VSAGLevel Voltage Sag Level Threshold Register. 24 11000 VSAGDuration Voltage Sag Duration Register. 25 11001 Res Reserved † 26 11010 Mask Mask Register 27 11011 Res Reserved † 28 11100 Ctrl Control Register 29 11101 Res Reserved † 30 11110 Res Reserved † 31 11111 Res Reserved † † These registers are for internal use only. For proper device operation, the user must not attempt to write to these registers. B7 B6 B5 B4 B3 B2 B1 B0 0W/R RA4 RA3 RA2 RA1 RA0 0 |
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